Electromigration Modeling At Circuit Layout Level 2013th Edition Cher Ming Tan by Cher Ming Tan, Feifei He 9789814451208, 9814451207 instant download after payment.

Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level.
Table of Contents
Cover
Electromigration Modeling at Circuit Layout Level
ISBN 9789814451208 ISBN 9789814451215
Preface
Contents
Symbols
Chapter 1 Introduction
1.1 Overview of Electromigration
1.2 Modeling of Electromigration
1.3 Organization of the Book
1.4 Summary
Chapter 2 3D Circuit Model Construction and Simulation
2.1 Introduction
2.2 Layout Extraction and 3D Model Construction
2.3 Transient Electro-Thermo-Structural Simulations and Atomic Flux Divergence Computation
2.3.1 Transient Thermal-Electric Analysis
o 2.3.1.1 Boundary Conditions
o 2.3.1.2 Electrical Loads
o 2.3.1.3 Application of the Electrical Loads
2.3.2 Transient Structural-Thermal Analysis
o 2.3.2.1 Boundary Conditions
o 2.3.2.2 Thermal Loads
2.3.3 Application of Submodeling
2.3.4 Computation of Atomic Flux Divergences
2.4 Simulation Results and Discussions 2.4.1 Current Density and Temperature Distributions
2.4.2 Transient Temperature Variation During Circuit Operation
2.4.3 Effect of the Substrate Dimension on the Circuit Temperature
2.4.4 Transient Thermo-Mechanical Stress Variation During Circuit Operation
2.4.5 Distributions of the Atomic Flux Divergences
2.5 Effects of Barrier Thickness and Low-j Dielectric on Circuit EM Reliability
2.6 Summary
Chapter 3 Comparison of EM Performances in Circuit and Test Structures
3.1 Introduction
3.2 Model Construction and Simulation Setup
3.3 Distributions of Atomic Flux Divergences Under Different Operation Conditions
3.4 Effects of Interconnect Structures on Circuit EM Reliability
3.5 Effects of Transistor Finger Number on Circuit EM Reliability
3.6 Summary
Chapter 4 Interconnect EM Reliability Modeling at Circuit Layout Level
4.1 Introduction
4.2 Model Construction and Simulation Setup
4.3 Distributions of Atomic Flux Divergences 4.3.1 Total AFD Distribution of the Full Model
4.3.2 Total AFD Distribution of the Sub-Model
4.4 Effects of Layout and Process Parameters on Circuit EM Reliability
4.4.1 Line Width and Degree of Turning
4.4.2 Transistor Orientation
4.4.3 Inter-Transistor Distance
4.4.4 Stress-Free Temperature of the Metallization
4.5 Summary
Chapter 5 Concluding Remarks
5.1 Conclusions
5.2 Recommendations for Future Work