Full Chip Nanometer Routing Techniques 1st edition by Ho ISBN 1402061943 978-1402061943 by Tsung-yi Ho, Yao-wen Chang, Sao-jie Chen 1402061943 instant download after payment.

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ISBN 10: 1402061943
ISBN 13: 978-1402061943
Author: Ho 

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.

In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Full-Chip Nanometer Routing Techniques 1st Table of contents:

Chapter1 : Introduction

Chapter 2: Content

Chapter 3: Conclusion 

Chapter 4: Appendices

Chapter 5: Glossary

Chapter 6: References 

Chapter 7: Index

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Tags: Ho, Nanometer Routing