Wafer Level 3d Ics Process Technology 1st Edition Chuan Seng Tan by Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif (auth.), Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif (eds.) 9780387765327, 9780387765341, 0387765328, 0387765344 instant download after payment.

Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration.

Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration.