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Low Power Interconnect Design 1st Edition Sandeep Saini Auth

  • SKU: BELL-5139896
Low Power Interconnect Design 1st Edition Sandeep Saini Auth
$ 31.00 $ 45.00 (-31%)

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Low Power Interconnect Design 1st Edition Sandeep Saini Auth instant download after payment.

Publisher: Springer-Verlag New York
File Extension: PDF
File size: 4.82 MB
Pages: 152
Author: Sandeep Saini (auth.)
ISBN: 9781461413226, 1461413222
Language: English
Year: 2015
Edition: 1

Product desciption

Low Power Interconnect Design 1st Edition Sandeep Saini Auth by Sandeep Saini (auth.) 9781461413226, 1461413222 instant download after payment.

This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.

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